RoRD Project Plan Report

This report organizes the paper submission plan and follow-up optimization work for the RoRD project. The core goal is to build a multi-round submission strategy around an expected paper completion date in April 2026, while planning technical optimization across data, model architecture, training, inference, and evaluation.

Paper Submission Plan

Major Conference Timeline

The following are typical submission timelines for major EDA conferences.

Conference	Submission deadline	Notification	Conference date
ICCAD	Mid to late May	Early August	Late October to early November
DAC	Mid to late November	Late February to early March next year	June to July next year
ASP-DAC	Mid July	Mid to late October	Late January next year
DATE	Mid September	Mid December	March to April next year

Multi-Stage Submission Strategy

Based on the expected paper completion date in April 2026, this project follows a multi-round submission strategy with backup options. Reviews from each round will be used to improve the next version.

Stage	Time	Target venue	Strategy
First attempt	Spring 2026	ICCAD 2026	Finish in April, submit in May, receive reviews in August.
Second attempt, Plan A	Fall 2026	DATE 2027	Submit in September; tight schedule, suitable if there are clear improvements from May to August.
Second attempt, Plan B	Fall 2026	DAC 2027	Submit in November; three months for revision and extra experiments.
Third attempt	Spring to summer 2027	ASP-DAC 2028	Revise from March to July and submit in July with higher quality.
Follow-up plan	After 2027	IEEE TCAD	Convert to a journal paper with a more complete and polished story.

Stage Notes

1. First attempt: ICCAD 2026
   The schedule is April completion, mid to late May submission, and early August notification. This is the first target and the ideal top-conference outcome.

2. Second attempt: dual-track plan
   Plan A is DATE 2027, with a mid-September deadline and limited revision time. Plan B is DAC 2027, with a mid to late November deadline and a longer revision window for adding key experiments.

3. Third attempt: ASP-DAC 2028
   After two rounds of top-conference feedback, the paper should be significantly improved. The March-to-July revision window provides enough time for further polishing.

4. Follow-up plan: journal submission
   If the paper is not accepted after several conference attempts, it can be expanded and submitted to a journal such as IEEE TCAD.

Follow-Up Optimization Overview

To improve the performance and practicality of the RoRD model, optimization tasks are organized by module, priority, and status.

Module	Task	Priority	Status	Value
Data strategy and augmentation	Introduce elastic transformations	High	Pending	Simulate small physical deformations in chip manufacturing.
Data strategy and augmentation	Create a synthetic layout data generator	High	Pending	Address real-data scarcity.
Model architecture	Experiment with modern backbones	Medium	Pending	Replace VGG-16 with ResNet or EfficientNet.
Model architecture	Integrate attention mechanisms	Medium	Pending	Focus on key geometric structures and improve feature quality.
Training and loss functions	Implement automatic loss weighting	High	Pending	Automatically balance multi-task optimization difficulty.
Training and loss functions	Hard sample mining	Medium	Pending	Improve descriptor learning efficiency.
Inference and matching	Feature Pyramid Network (FPN)	High	Completed	Obtain multi-scale features in one forward pass.
Inference and matching	Keypoint deduplication (NMS)	Medium	Completed	Remove duplicate keypoints from sliding windows.
Code and project structure	Move configuration to YAML	Low	Completed	Manage multiple experiment configurations more easily.
Code and project structure	Decouple code modules	Low	Completed	Improve maintainability.
Experiment tracking and evaluation	Integrate TensorBoard / W&B	Medium	Completed	Monitor experiment results in real time.
Experiment tracking and evaluation	Add mAP metrics	Medium	Completed	Provide more comprehensive performance evaluation.

Data Strategy And Augmentation

Module Goal

Improve robustness and generalization while reducing dependence on large amounts of real data.

Introduce Elastic Transformations

Priority: high.

Value: simulate small physical deformations that may occur during chip manufacturing, making the model more robust to non-rigid variation.

Execution plan:

1. Add albumentations as a project dependency.
2. Integrate augmentation into the ICLayoutTrainingDataset class in train.py.
3. Configure A.ElasticTransform in the augmentation pipeline.

Create A Synthetic Layout Data Generator

Priority: high.

Value: address the difficulty and scarcity of real layout data by programmatically generating many diverse training samples.

Execution plan:

1. Create a new script named tools/generate_synthetic_layouts.py.
2. Use gdstk to programmatically generate GDSII files.
3. Use tools/layout2png.py to batch-convert the generated layouts into PNG images.

Model Architecture Optimization

Module Goal

Improve feature extraction efficiency and accuracy while reducing computational cost.

Experiment With Modern Backbones

Priority: medium.

Value: VGG-16 is classic but inefficient. ResNet and EfficientNet may provide better performance with fewer parameters and less computation.

Execution plan:

1. Modify the __init__ method of the RoRD class in models/rord.py.
2. Replace vgg16 with models from torchvision.models.
3. Try resnet34 or efficientnet_b0.
4. Adjust input channel sizes for the detector head and descriptor head.

Integrate Attention Mechanisms

Priority: medium.

Value: guide the model to focus on key layout geometry such as corners and intersections, while ignoring large blank or repetitive regions.

Execution plan:

1. Select a reliable attention module such as CBAM or SE-Net.
2. Insert the attention module into models/rord.py.
3. Place it between self.backbone and the two heads.

Training Resource Requirements

Resource Configuration

Resource type	Requirement	Notes
Dataset, startup phase	100 to 200 images	High-resolution layouts for functional validation.
Dataset, initial usable model	1,000 to 2,000 images	Learn robust geometric features.
Dataset, production level	5,000 to 10,000+ images	Cover different processes and design styles.
Entry-level GPU	RTX 3060 / 4060	Basic training requirement.
Mainstream GPU	RTX 3080 / 4070	Recommended setup.
Professional GPU	RTX 3090 / 4090 / A6000	Best performance.
VRAM	>= 12GB	Batch Size = 8, Patch = 256x256.
CPU / memory	8 cores / 32GB	Avoid data preprocessing bottlenecks.

Time Estimate And Tuning Plan

Training stage	Time estimate	Notes
Single epoch	15 to 25 minutes	RTX 3080, 2000 images.
Total training time	About 16.7 hours	50 epochs at 20 minutes per epoch.
Practical convergence time	10 to 20 hours	With early stopping, patience = 10.
Augmentation tuning	1 to 2 weeks	Tune scale, brightness, and noise.
Loss-weight tuning	1 to 2 weeks	Balance BCE, Triplet, Manhattan, and related terms.
Hyperparameter search	2 to 4 weeks	Tune learning rate, batch size, and optimizer.
Architecture tuning	2 to 4 weeks	Try different backbones.
Total tuning time	1.5 to 3 months	Reach production-level quality.

Summary

This plan splits the work into two parallel tracks: paper publication and engineering optimization. The publication track uses multiple conference attempts with a journal backup plan. The technical track prioritizes data generation, augmentation, automatic loss weighting, hard sample mining, and modern feature extraction. This keeps short-term deliverables visible while leaving room for long-term model-quality improvements.