RoRD Graduation Project: Structure-Aware Local Feature Matching for IC Layouts

A graduation-project summary of the RoRD layout recognition pipeline, covering structure-aware four-channel inputs, joint keypoint and descriptor learning, large-layout retrieval, RANSAC verification, and iterative multi-instance search.

RoRD Midterm Review: Rotation-Robust Descriptors For IC Layout Recognition

Midterm progress report for RoRD-Layout-Recognition, covering project overview, completion analysis, core features, performance testing, innovations, and future plan.

RoRD Implementation And Benchmark Report

Summary of new RoRD features: ElasticTransform, procedural and diffusion synthesis, three-source mixed training, one-command pipeline, and ResNet34 + FPN benchmark analysis.

RoRD-Layout-Recognation Comprehensive Technical Report

A full technical summary of RoRD-Layout-Recognation: project history, architecture, key innovations, current outcomes, and future planning.

RoRD Project Plan Report: Submission Strategy And Follow-Up Optimization

RoRD project planning report for September 28, 2025, covering paper submission strategy, optimization roadmap, training resources, and tuning timeline.

Geo-Layout Transformer: A Self-Supervised Foundation Model For Physical Design Analysis

Technical report on Geo-Layout Transformer, a GNN and Transformer based foundation model for IC layout analysis.